Analog-to-digital converters (ADCs) are used for a wide range of applications, including, but not limited to, sensor interfaces, industrial applications, consumer applications, and communications. Various circuits and techniques have been developed for analog-to-digital (A/D) conversion targeting various applications and their varying requirements in terms of speed, resolution, noise, power consumption, and other performance related parameters. Precision low-noise ADCs may be configured for receiving and converting fully-differential input signals with only little common-mode variation allowed. An interface circuit may be required to transform, for example, a single-ended analog input signal to a fully-differential analog signal suitable for interfacing a fully-differential circuit.
FIG. 1 shows an exemplary ADC circuit 100, comprising an interface circuit 101 and a fully-differential ADC 102. ADC circuit 100 may be configured to receive a single-ended input signal VIP within a full-scale range from (−2*VREF) to (+2*VREF), where VREF may be provided by a reference-voltage source 103. For example, VREF may be 5V, and a full-scale range of ADC circuit 100 may be from (−10V) to (+10V). VIN may be biased at a reference potential (ground), VIN=GND, when ADC circuit 100 is configured to convert a single-ended input signal VIP=V(VIP,GND). ADC circuit 100 may be configured such that VIP=(−2*VREF) corresponds to a numerical value d(k)=(−1) and such that VIP=(+2*VREF) corresponds to d(k)=(+1). An idealized behavior may thus be described as d(k)=VIP/(2*VREF) for any input voltage VIP within a full-scale input range.
Fully-differential ADC 102 may be configured to sample two single-ended voltages, VP and VN, at a first ADC input terminal 104 and a second ADC input terminal 105, respectively. The fully-differential ADC 102 may provide numerical values d(k) that nominally represent a difference V(VP,VN)=VP−VN of the sampled voltages VP and VN normalized to the reference voltage VREF, which may be described as d(k)=V(VP,VN)/VREF. For single-ended signals, VP=V(VP,GND) and VN=V(VN,GND). For example, for VREF=5V, VP=4V, and VN=1V, a nominal response may be d(k)=V(VP,VN)/VREF=(4V−1V)/5V=0.6. The fully-differential ADC 102 may require that a common-mode voltage VCM=(VP+VN)/2 be close to a nominal value, say VREF/2. For example, it may be required that (VP+VN) be at least VREF-0.2V, and no more than VREF+0.2V. When a common-mode requirement is fulfilled, the fully-differential ADC 102 may provide good common-mode rejection, such that numerical values d(k) are substantially independent of common-mode voltage VCM and almost exclusively represent sampled voltage differences V(VP,VN).
Interface circuit 101 of FIG. 1 may be implemented using a differential amplifier 106 configured as shown in FIG. 2. Resistors RN1, RP2 are configured to provide at an inverting amplifier input terminal 107, a weighted average of an applied input voltage VIN and a first output voltage VP provided by differential amplifier 106 at a non-inverting first output terminal 104. Likewise, resistors RP1, RN2 are configured to provide at a non-inverting amplifier input terminal 108, a weighted average of an applied voltage VIP and a second output voltage VN provided by differential amplifier 106 at an inverting second output terminal 105. Accordingly, resistors RN1, RP2, RP1, and RN2 are configured to provide negative feedback for differential amplifier 106. Differential amplifier 106 may be configured to provide a very large differential gain ADIFF for voltage differences from amplifier input terminals 107, 108 to output terminals 104, 105, such that, provided stability and non-overload operation, amplifier input terminals 107, 108 may have an only very small voltage difference across them. Differential amplifier 106 may be said to provide a “virtual short” between amplifier input terminals 107, 108 when the differential gain ADIFF approaches infinity. The virtual short may exist (in approximation) for any common voltage on amplifier input terminals 107, 108. Differential amplifier 106 may be configured such that an output common-mode voltage VCM=(VP+VN)/2 is regulated to be nominally the same as an applied control voltage VC. For example, a control voltage VC=VREF/2 may be applied to fulfill a common-mode requirement when driving a fully-differential ADC (a terminal for applying control voltage VC is not shown explicitly in FIG. 1). Accordingly, interface circuit 101 of FIG. 2 may provide an output common-mode voltage VCM=(VP+VN)/2 that is substantially the same as an applied control voltage VC, and an output voltage difference V(VP,VN) that is substantially set by an input voltage difference V(VIP,VIN) and selected values of resistors RN1, RP2, RP1, and RN2. In one exemplary embodiment, it may be selected that RN1=RP1=R1 and RP2=RN2=R2, and a nominal behavior may be described as V(VP,VN)=(R2/R1)*V(VIP,VIN) and VCM=(VP+VN)/2=VC=VREF/2.
Differential amplifier 106 will be subject to real-world imperfections, such as finite gain, nonlinear gain, finite bandwidth, nonlinear bandwidth, non-zero offset, non-zero thermal and flicker-type noise etc. Accordingly, a virtual short of amplifier input terminals 107, 108 will not be perfect, and output voltage difference V(VP,VN) may be distorted with respect to an ideal value (R2/R1)*V(VIP,VIN). ADC 102 (FIG. 1) may evaluate V(VP,VN) and provide a numerical representation d(k) thereof with an accuracy that may be in the order of one part-per-million (1 ppm). Differential amplifier 106 used to implement prior-art interface circuit 101 (FIG. 2) may be required to provide a differential gain ADIFF of more than 1 million to ensure an overall similarly high degree of accuracy. Likewise, an offset of differential amplifier 106 may have to be less than VREF/1,000,000. Noise from differential amplifier 106 will combine with noise from resistors RN1, RP2, RP1, RN2, and result in a level of noise in output voltage difference V(VP,VN) that exceeds a level of noise from the resistors alone. Accordingly, it may be very difficult to provide a differential amplifier 106 for prior-art interface circuit 101 (FIG. 2) that can live up to the performance and accuracy provided by some state-of-the-art ADCs 102 (FIG. 1).
Therefore, there is a need for an interface circuit that would be able to transform a first and a second input voltage VIP,VIN to a first and a second output voltage VP,VN for driving a fully-differential ADC with a selected common-mode voltage VCM=(VP+VN)/2, such that an accuracy of overall ADC circuit, such as the circuit 100, is commensurate with that of a fully-differential ADC, such as the circuit 102.
Further, there is a need for an interface circuit that would be able to transform single-ended voltages VIP=V(VIP,GND)=V(VIP,VIN) as well as generic-type voltage differences V(VIP,VIN) for which a common-mode voltage (VIP+VIN)/2 may not be tightly specified or controlled.